0 – July. 1. Qualification Package. AT89C51ED2. FLASH 8-bit C51 Microcontroller. 64 Kbytes FLASH, 2 Kbytes EEPROM. AT89C51RD2 / AT89C51ED2. AT89C51ED2-SLSUM Microchip Technology / Atmel 8-bit Microcontrollers – MCU 64kB Flash B RAM VV datasheet, inventory, & pricing. AT89C51ED2-SLSIM Microchip Technology / Atmel 8-bit Microcontrollers – MCU 80C31 w/4k datasheet, inventory, & pricing.
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Page 38 Table Page 8 Table Timer 2 operation is similar to Timer 0 and Timer 1. All other vectors addresses are the same as standard C52 devices.
MICROCHIP TECHNOLOGY AT89C51ED2-SLRUM : Datasheet
Page 46 Figure It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. Set to enable timer 2 overflow interrupt.
Symbol Description Symbol Table It is based on 8 inputs with programmable interrupt capability on both high or low level.
A cold start reset is the one induced by VCC switch-on. This can be useful if external peripherals are mapped at addresses already used by the internal XRAM. To at8c51ed2 with slave A only, the master must send an address where bit 0 is clear e.
Document Revision History Page 74 Table Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic att89c51ed2. CF may be set by either hardware or software but can only be cleared by software.
Figure gives a logical view of the above statements. Set to enable all interrupts. Cleared to select 6 clock periods per peripheral clock cycle. Page Port 0: Do not set this bit 5 – Reserved The value read from this bit is indeterminate.
Set to enable KBF. Only one Master SPI device can initiate transmissions. Power-Down mode stops the oscillator, freezes all clock at known states.
Page 18 Figure Save and disable interrupts. ISP allows devices to alter their own program memory in the actual end product under software control.
The programming voltage is internally generated from the standard VCC pin. Page 62 Table RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to V CC as shown in Figure At89c51sd2 to enable SPI interrupt. Set to enable a high level detection on Port line 6.
This is the power supply voltage for normal, idle and power-down operation P0. Page 32 It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. Added Flash write programming time specification. This signal must stay low for any message for a Slave. In this mode, program execution halts. Set to enable a high level detection on Port line 7.
AT89C51ED2 – Microcontrollers and Processors – Microcontrollers and Processors
Oscillator To optimize the power consumption and execution time needed for a specific task, an internal prescaler feature has been implemented between the oscillator and the CPU and peripherals. The dual DPTR structure is a way by which the chip will specify the address of datasheeh external data memory location.
Page 78 Table This bit is set by hardware when a transfer has been completed. Set to program PCA to be gated off during idle. Ordering Information Table These API are executed by the bootloader. The external CEX input for the module on port 1 is sampled for a datasgeet.